Import uvm_pkg ::* `include "uvm_macros.svh" module top timeunit 1ns timeprecision 100ps bit clk, a, b default clocking ( posedge clk ) endclocking initial forever # 10 clk =!clk initial begin * VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115ģ) "Using SVA for scoreboarding and TB designs"Ĥ) "Assertions Instead of FSMs/logic for Scoreboarding and Verification" * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1 * Component Design by Example ", 2001 ISBN 0-970 * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712 * Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-970 * A Pragmatic Approach to VMM Adoption 2006 ISBN 0-970 Write loop to do the check and report errorĮndtask // This approach gives you all the flexibility and features of SystemVerilogįor training, consulting, services: contact
By consuming 1 WrClk cycle the assertion would miss to detect such scenarios.īelow code is almost same as having an external logic having 1 WrClk delay.Īlways ( posedge WrClk ) // local variables for last write if (WrEn, Addr = WrAddr & lastwrite ) fork test_task ( ) join_none task automatic test_task ( ) The ultimate objective of the assertion is to detect read/write overlap. Note: I cannot have an external logic to derive the LastWrEn, LastWrAddr as this would consume atleast 1 WrClk cycle. How to filter the last write on the LHS? I'm looking of something like/equivalent to 'last_match'. Only the assertion-instance for the last write cycle (where the complete stable data is available) passes. The above assertion fails as my DUT might initiate multiple writes to the same address continuously with incremental data (say usually across 2 or 3 clock cycles).But the read for a given address will always be for 1 clockĪs a result, 2 or 3 instance of same assertion gets spawned for every write cycle for the same address. It is my DUT which initiates Write and Read.
Property data_integrity_check ( ) logic Addr logic Data ( posedge WrClk ) (WrEn, Addr = WrAddr, Data = WrData ) |-> ( posedge RdClk ) first_match ( # (RdEn & (RdAddr = Addr ) ) ) # 1 (RdData = Data ) endproperty :data_integrity_check
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